1. Field of the Invention
The present invention relates to a failure analysis device and a memory device measuring device for an IC tester. In particular, the present invention reduces the memory capacity of an internal memory in the failure analysis device and performs an address translation for the stored failure data of the internal memory regardless of an increase in memory capacity of the memory device and complication of an address decoder circuit.
2. Description of Related Art
A memory device measuring device for an IC tester shown in FIG. 6 is known as a conventional device.
The memory device measuring device shown in FIG. 6 comprises a timing generator 2, a pattern generator 3, a driver 4, a device 5 to be measured, a comparator 6, a failure analysis device 70, and the like.
The timing generator 2 outputs a clock signal to the driver 4 and outputs a strobe signal to the comparator 6. The pattern generator 3 outputs a write pattern signal to the driver 4 and the comparator 6, and outputs X and Y address signals to the driver 4 and the failure analysis device 70.
The driver 4 outputs a device address to the device 5 to be measured and writes the device write pattern corresponding to the device address to the device 5 on the basis of the clock signal received from the timing generator 2, the write pattern signal received from the pattern generator 3 and the X and Y address signals received from the pattern generator 3.
The comparator 6 compares the write pattern signal received from the pattern generator 3 as an expected pattern with device readout pattern received from the device 5 to be measured, on the basis of the strobe signal received from the timing generator 2. When one pattern does not coincide with the other, the comparator 6 outputs a failure data to the failure analysis device 70.
The failure analysis device 70 stores the failure data received from the comparator 6 in the internal memory 7D thereof corresponding to the address assigned by the X and Y address signals received from the pattern generator 3.
FIG. 7 is a block diagram showing a concrete composition of the above-mentioned failure analysis device.
The failure analysis device 70 shown in FIG. 7 comprises an n-bit shift matrix circuit 7B, an internal circuit 7D, a decode circuit 7F to increase the memory capacity of the internal memory 7D, and the like. Further, reference numeral 73 designates a memory address (line) of the internal memory 7D which is connected with a CPU (not shown) through a CPU bus 72.
The n-bit shift matrix circuit 7B outputs the X and Y address received from the pattern generator 3 shown in FIG. 6 as the memory address 73 obtained by shifting the Y address for the number of the effective bits of the X address and by incorporating one address into the other, and stores the failure data received from the comparator 6 in the internal memory 7D by using a write enable terminal (WE) of the internal memory 7D when the failure data is detected. The CPU (not shown) fetches the failure data stored in the internal memory 7D through the CPU bus 72 in order to carry out the failure analysis.
However, according to the composition of the failure analysis device shown in FIG. 7, there is a problem that when the device address space of the device 5 to be measured is larger than the memory address space of the internal memory 7D, the failure analysis device 70 fetches the failure data into the internal memory 7D thereof and analyzes the data several times.
Further, when the bits used for the X and Y address of the device 5 to be measured are not consecutive, the area of the internal memory 7D, in which the failure data is stored is divided into several sections. Therefore, there is a problem that when the failure data of the internal memory 7D is fetched to the CPU, it takes longer to read all of the memory space of the internal memory 7D.